Design For Test (DFT) / DFx Methodology and Architecture Lead
AMD · Santa Clara, CA · Engineering
About this role
AMD is hiring a senior-level Hardware Engineer in the software engineering function based in Santa Clara, CA. The posting calls out experience with Python, Testing, Observability, Frontend Development.
- Role
- Hardware Engineer
- Function
- software engineering
- Level
- senior
- Track
- Individual contributor
- Location
- Santa Clara, CA
- Department
- Engineering
- Posted
- May 18, 2026
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Job description
from AMD careersWHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
HE ROLE:
The Circuit Technology team is looking for a passionate and experienced DFT/DFx Methodology, Architecture, and RTL Execution Lead to support high-speed SerDes PHYs, next-generation Memory PHYs, and die-to-die interconnect IPs.
In this role, you will own and drive DFT/DFx architecture definition, RTL implementation, methodology development, scan integration support, test constraints, ATPG support, and post-silicon debug for advanced PHY and connectivity IP designs. You will work closely with design, verification, physical design, CAD, product engineering, and test engineering teams to deliver robust, high-coverage, production-ready IP.