About this role

IBM is hiring a mid-level Hardware Engineer in the software engineering function based in Bangalore, IN. The posting calls out experience with Linux, Agile, DevOps, Performance Optimization and roughly 6+ years of relevant work.

Role: Hardware Engineer
Function: software engineering
Level: mid
Track: Individual contributor
Employment: Full-time
Location: Bangalore, IN
Experience: 6+ years
Department: Infrastructure & Technology

AI Summary

Design and integrate PCIe/CXL logic for IBM's high-performance processors. Develop microarchitecture, RTL, and manage cross-functional collaboration with verification and physical design teams. Requires 6+ years in high-speed data transfer protocol design with processor silicon bring-up experience.

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Job description

from IBM careers

Introduction

At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security, and scalability that clients and industries depend on every day. Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration. You’ll work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation. With continuous learning, career growth, and a supportive culture, IBM provides the opportunities to build expertise and shape the infrastructure that drives progress.

Your role and responsibilities

- You will be working on the high-performance Processors of IBM Systems.
- Responsible for Design & Integration of PCIe/CXL logic for the high Speed Processors

- Develop the features, present the proposed architecture in the High level design discussions

- Estimate the overall effort to develop the feature.
- Estimate silicon area and wire usage for the feature.
- Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature
- Signoff the Pre-silicon Design that meets all the functional, area and timing goals
- Participate in post silicon lab bring-up and validation of the hardware
- Guide and mentor team members, represent as Logic Design team member in global forums.

Required technical and professional expertise

- 6-10 or more years of demonstrated experience in logic design of PCIe/CXL or any high speed data transfer protocols.
- Experience with solving timing, power, area and performance issues in high speed designs.

- At least 1 generation of Processor Core silicon bring up experience

- Good understanding of multiple facets of Microprocessor Designs (e.g., x86, ARM, or RISC-V processor designs)

- Proficiency of RTL design with Verilog or VHDL

Preferred technical and professional experience

- Working knowledge of verification principles

- Ability to read and understand Physical design reports for solving Timing, Area, Power and Performance issues through logic design changes.

- High-level knowledge of Linux operating system

- Knowledge of one object oriented language and scripting language
- Understanding of Agile development processes
- Experience with DevOps design methodologies and tools