ASIC Physical Design Engineer
Cisco · Maynard, MA · Product and Engineering
About this role
Cisco is hiring a mid-level Hardware Engineer in the software engineering function based in Maynard, MA. The posting calls out experience with Python, Testing, Performance Optimization. Compensation is listed at $135,800–$195,100 per year.
- Role
- Hardware Engineer
- Function
- software engineering
- Level
- mid
- Track
- Individual contributor
- Employment
- Full-time
- Location
- Maynard, MA
- Department
- Product and Engineering
- Posted
- May 19, 2026
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Job description
from Cisco careersJob posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
Meet the Team
Acacia, part of Cisco, provides innovative silicon-based high-speed optical interconnect products to accelerate network scalability through advancements in performance, capacity, and cost. Our DSP ASICs, silicon photonic PICs, and coherent modules empower cloud and service providers to meet the fast-growing demand for data. We have assembled a team of cross-functional experts capable of solving the challenges of next-generation optical interconnects, resulting in industry-leading, award-winning products. Come join us at Cisco, named the #1 world’s best workplaces, and do purposeful work that makes a global impact and gives back to a company culture that empowers an inclusive future for all.
Your Impact
As a Physical Design Engineer with Acacia, you will focus on the technical execution of high-performance ASIC designs. Working as an individual contributor, you will lead the RTL-to-GDSII implementation flow for advanced semiconductor nodes, ensuring that Acacia’s networking platforms meet rigorous power, performance, and area (PPA) targets. You will be responsible for the successful delivery of assigned blocks from specification through to tapeout.
Implement end-to-end RTL-to-GDSII implementation for advanced nodes (sub-7nm to 2nm)
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