Design Enablement Engineer II

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Key responsibilities

• Leverage silicon verification platform and environment to create necessary post-silicon infrastructure, methodology and automation to allow tests executed in a timely and efficient manner.
• Integrate silicon, HW, firmware, and system software into a complete system which includes various InfiniBand and PCIe protocols, PXE booting, virtual machines, secure networks, Ethernet and Ethernet-over-InfiniBand, sockets and RPC calls, FPGA, microcontroller interfaces, JTAG, I2C, SPI, SERDES, memory and many other interfaces.
• Execute post-silicon tests to expose design issues, validate product against the specifications including performance, and qualify the design for production release.
• Review, replicate, and respond to customer issues. Perform initial analysis of error logs from customer design simulation runs. Debug and isolate system-level issues down to ASIC/FPGAs, host servers, subsystems, firmware modules, runtime diagnostics.
• Develop silicon and system stress tests. Leverage tests developed by other engineers. Package tests for production and field use.
• Define, develop and drive the implementation of validation automation environment

Requirement

• Bachelor’s degree in Electrical Engineering or Computer Engineering. Master’s degree preferred.
• Must be proficient in one or more of the following disciplines – silicon simulation, silicon design, HW design, firmware design, silicon bring-up, system bring-up, HW/SW debug, verification and validation.
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