Principal Application Engineer

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Description:
• Work closely with Sales team to identify and scope opportunities for Cadence Emulation and Prototyping products.
• Plan, execute and manage key technical evaluations and benchmark with existing and potential customers.
• Train, ramp-up and accompany customer project.
• Conduct basic and advanced trainings, presentations and demos as necessary.
• Providing technical expertise to address clients’ queries, which need expert involvement.
• Aligned closely with corporate engineering and sales/marketing team on customer requirement for product direction/improvement.

Position Requirements:
• Minimum 8 years hands-on expertise on SoC design & verification technique
• Design experience in Verilog/VHDL for IP or SoC chip level is required
• Knowledge of System Verilog/VHDL and HDL simulators is required
• Experience with hardware emulator or FPGA prototyping is a big advantage
• Knowledge of Unix and Linux is highly desired
• Familiar with shell/python/tcl etc. script language is a plus
• Advanced Verification Methodology like UVM is a plus
• Strong verbal and written communication skills in English
• Strong teamwork skills with good human relationship
• Ability to travel within Asia Pacific region for onsite customer visits is a plus.