Sr Principal Product Engineer – Memory IP
Cadence Design Systems · San Jose, CA
About this role
Cadence Design Systems is hiring a senior-level Manufacturing Engineer in the operations function based in San Jose, CA. The posting calls out experience with System Design, Data Analytics and roughly 7+ years of relevant work. Listed education preference: a master's degree or equivalent. Compensation is listed at $154,000–$286,000 per year.
- Role
- Manufacturing Engineer
- Function
- operations
- Level
- senior
- Track
- Tech leadership
- Employment
- Full-time
- Location
- San Jose, CA
- Experience
- 7+ years
- Education
- Master's degree
- Posted
- Apr 20, 2026
More roles at Cadence Design Systems
Job description
from Cadence Design Systems careersAt Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
About Us
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. We apply our Intelligent System Design strategy to deliver software, hardware, and IP that turn design concepts into reality. Our customers are the world’s most innovative companies, delivering extraordinary electronic products—from chips to boards to systems—for dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial, and health. Join us and be part of a culture that values innovation, collaboration, and customer success.
Position Overview
Join our growing and dynamic IP team and help lead the proliferation of best-in-class Memory PHY IP products across a wide range of customers. This is a tremendous opportunity to work with an experienced team focused on the development and support of high-performance IP related to memory protocols such as DDR, LPDDR, HBM, and GDDR, and to engage with top technology companies making an impact in our world.
We are seeking a Post Silicon Memory Product Engineer to support silicon bring-up, debug, and production ramp for advanced memory IP solutions. This role is critical in ensuring successful integration of Memory PHY and Controller IP into customer systems.