Lead Hardware Engineer - DFT IP R&D
Cadence Design Systems · Noida, India
About this role
Cadence Design Systems is hiring a senior-level Hardware Engineer in the software engineering function based in Noida, India. The posting calls out experience with Python, Data Structures, Frontend Development, Design Systems and roughly 4–6 years of relevant work. Listed education preference: a bachelor's degree or equivalent.
- Role
- Hardware Engineer
- Function
- software engineering
- Level
- senior
- Track
- Individual contributor
- Employment
- Full-time
- Location
- Noida, India
- Experience
- 4–6 years
- Education
- Bachelor's degree
- Posted
- Apr 20, 2026
More roles at Cadence Design Systems
Job description
from Cadence Design Systems careersAt Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Position: Lead Hardware Engineer - DFT IP R&D
Location: Noida
Experience: 4-6 Years
Job Description
Cadence Design Systems is looking for a highly motivated software and hardware engineer to work as a member of the R&D staff on Cadence’s MODUS DFT software solution. MODUS is a complete product that encompasses Design for Test Solution for Achieving High Coverage, Reduced Test Time, and Superior PPA. The product breadth means we are looking for skilled and motivated candidates with backgrounds in RTL design, DFT architecture, computer architecture, verification, RTL compilation, placement, static timing analysis, power analysis, routing, extraction, and optimization. You will be part of a team responsible for creating the innovative technologies required for technology leadership in the DFT space. This position will encourage building of a solid foundation in logic circuits and gentle entry into larger DFT IP tool development. Development responsibilities include designing, developing, troubleshooting, debugging and supporting the MODUS software product.
Job Responsibilities:
You will play a key role in developing cutting-edge design-for-testability (DFT) tools, contributing to improved usability and quality through feature enhancement and rigorous verification. The role’s day to day responsibilities cover: