DSP or Serdes RTL Sr Principal Digital Design Engineer
Cadence Design Systems · San Jose, CA
About this role
Cadence Design Systems is hiring a senior-level Hardware Engineer in the software engineering function based in San Jose, CA. The posting calls out experience with Data Structures, Embedded Systems, Frontend Development and roughly 10+ years of relevant work. Compensation is listed at $154,000–$286,000 per year.
- Role
- Hardware Engineer
- Function
- software engineering
- Level
- senior
- Track
- Tech leadership
- Employment
- Full-time
- Location
- San Jose, CA
- Work mode
- On-site
- Experience
- 10+ years
- Posted
- Apr 20, 2026
More roles at Cadence Design Systems
Job description
from Cadence Design Systems careersAt Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
This is an opportunity to join a dynamic and growing team of engineers developing high-speed PMA layer IP for industry-standard protocols. The successful candidate will be a highly self-motivated and results-oriented member of a small team of engineers that can learn and improve existing digital flows. The candidate will primarily be responsible for front-end coding, scripting and developing flows at all phases of the digital design and functional verification. It is further expected that the candidate will be able to work as part of a small and focused team of engineers and will be able to collaborate successfully as needed with the digital, analog and application teams. Candidate should be willing to work full time in the San Jose office. A Cadence satellite office (if senior with extensive SerDes exp.) will be considered.
Position Requirements
This team is focused on DSP and/or High Speed Serdes. The ideal candidate will have at least 10 plus years of actual work experience in SerDes as well as a thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status. This includes but is not limited to: