mid sales Partnerships Manager ic Bachelor's · Posted Apr 7, 2026

About this role

AMD is hiring a mid-level Partnerships Manager in the sales function based in Bangalore, India. The posting calls out experience with Machine Learning, Embedded Systems, ETL. Listed education preference: a bachelor's degree or equivalent.

Role
Partnerships Manager
Function
sales
Level
mid
Track
Individual contributor
Location
Bangalore, India
Education
Bachelor's degree
Department
Engineering
Posted
Apr 7, 2026
AI Summary
Fellow-level Verification Architect defining verification architecture and methodology for high-speed interface PHY IP designs (DDR, LPDDR, USB, PCIe). Lead UVM testbench development, HW/SW co-verification flows, and AI-driven verification improvements across global teams. Requires deep expertise in advanced verification methodologies and strategic technical leadership.

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Job description

from AMD careers


WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  




 

Fellow – Verification Architect

Location: [Insert Location]
Job Category: Engineering – Technical Leadership
Career Track: Fellow (Technical Ladder)
Reports To: [Insert Hiring Manager]


The Role

At AMD, we push the boundaries of innovation. As a Fellow-level Verification Architect, you will define and lead the verification architecture and methodology for next-generation high-speed interface PHY IP designs (DDR, LPDDR, USB, PCIe, and emerging standards). You will set the strategic direction for complex UVM testbench architectures, drive methodology innovation (including HW/SW co-verification and AI-assisted flows), and ensure scalable, high-quality verification outcomes across global programs.

This is an excerpt. Read the full job description on AMD careers →
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