Processor ASIC RTL Design Engineer

Job description

##
Company:

Qualcomm Technologies, Inc.

## Job Area:

Engineering Group, Engineering Group > DSP Architecture and Design

General Summary:

A variety of high performance, low power Hexagon/NPU cores are at the heart of Qualcomm’s multi-tier mobile SOC, Server IoT, Automotive roadmap. The Hexagon architecture is designed to deliver performance with low power and area over a variety of applications like Audio, Modem, AI, IoT and Automotive.

This position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the challenges posed by advanced technologies. The successful candidate will possess detailed understanding of RTL design, synthesis, static timing analysis, PLDRC, clock domain crossing, and low power techniques. Knowledge and experience of microprocessor design and integration is a definite advantage.

The job responsibilities include:

* Work with system architecture team to define micro-architecture documentation for various blocks in Hexagon/NPU and sub-system
* Develop RTL for multiple logic blocks of Hexagon/NPU and sub-system for SoC integration
* Run various frontend tools to check for linting, clock domain crossing, power intent etc
* Work with physical design team on design constraints and timing closure
* Work on area and power optimization
* Work with verification team to collaborate on test plan, test debug, coverage plan and coverage closure
* Support internal hardware integration
* Provide ideas and further the innovation of ASICs, IP cores, and process flows