Lead DFT Engineer
NXP Semiconductors · Noida, India
About this role
NXP Semiconductors is hiring a senior-level Hardware Engineer in the software engineering function based in Noida, India. Listed education preference: a bachelor's degree or equivalent.
- Role
- Hardware Engineer
- Function
- software engineering
- Level
- senior
- Track
- Individual contributor
- Employment
- Full-time
- Location
- Noida, India
- Education
- Bachelor's degree
- Posted
- Jul 10, 2026
Job description
from NXP Semiconductors careersDigital Design Engineer with hand on experience in Scan insertion, ATPG, GLS. He/She will be responsible for understanding the DFT architecture of the design and providing the scan insertion collaterals to the implementation team, to enable scan insertion flows during synthesis. Should have proficiency in industry-standard DFT tools such as Mentor Tessent, Synopsys DFT Compiler, Cadence Encounter Test. Should be able to contribute to ATPG at partition and SoC level. . Should have experience with DFT GLS simulation tools and methodologies, including fault modeling and coverage analysis. Should be familiar with industry standards such as IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG). Effective communication and teamwork skills, with the ability to collaborate across functions.
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