senior Professional Services Consultant ic 5+ yrs Bachelor's · Posted Apr 20, 2026
$166,200 – $228,500
USD per year

About this role

NXP Semiconductors is hiring a senior-level Professional Services Consultant based in San Jose, CA. The posting calls out experience with Python, Testing, Automation and roughly 5+ years of relevant work. Listed education preference: a bachelor's degree or equivalent. Compensation is listed at $166,200–$228,500 per year.

Role
Professional Services Consultant
Function
services
Level
senior
Track
Individual contributor
Employment
Full-time
Location
San Jose, CA
Experience
5+ years
Education
Bachelor's degree
Posted
Apr 20, 2026
AI Summary
Senior Digital/AMS Design Engineer develops RTL for automotive SerDes transceivers, managing digital-analog integration from design through silicon validation. Requires 5+ years RTL design experience, SystemVerilog expertise, timing closure knowledge, and 40% lab validation work with Python scripting and high-speed debugging tools.

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Job description

from NXP Semiconductors careers

We are seeking a Senior Digital/AMS Design Engineer to drive the integration of complex digital logic into our industry-leading Automotive SerDes transceivers. In this role, you will be responsible for the RTL design of the "Digital-Analog Wrapper," ensuring seamless control and data flow between high-speed analog front-ends and the DSP/Link-layer logic. You will own the path from RTL through timing closure and support the validation of that logic in the lab.

Key Responsibilities

  • RTL Design & Integration: Develop and integrate RTL (Verilog/SystemVerilog) for control loops, calibration engines, and high-speed data paths in 10G+ transceivers.

  • Mixed-Signal Interface: Define and implement the digital interface for analog blocks (ADCs, PLLs, Driver stages), ensuring robust signal crossing between asynchronous domains.

  • Timing Closure & Synthesis: Lead the digital implementation flow, working closely with the physical design team to achieve timing closure in high-speed clock domains.

  • Silicon Validation: (40% Lab Focus) Partner with the validation team to bring up silicon. Use Python-based tools to exercise RTL features, debug state machines, and verify registers (CSRs) in real-time hardware.

  • Functional Correctness: Execute block-level and chip-level simulations to ensure digital control logic correctly handles analog PVT variations and startup sequences.

Skills & Qualifications

  • Education: BSEE/MSEE with 5–8+ years of experience in Digital RTL Design or Digital Integration.

    This is an excerpt. Read the full job description on NXP Semiconductors careers →
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