mid software engineering Hardware Engineer ic 5+ yrs Bachelor's
$125,000 – $291,000
USD per year

About this role

Neuralink is hiring a mid-level Hardware Engineer in the software engineering function based in Fremont, CA. The role typically asks for 5+ years of relevant experience. Listed education preference: a bachelor's degree or equivalent. Compensation is listed at $125,000–$291,000 per year.

Role
Hardware Engineer
Function
software engineering
Level
mid
Track
Individual contributor
Employment
Full-time
Location
Fremont, CA
Experience
5+ years
Education
Bachelor's degree
Department
Brain Interfaces Hardware
AI Summary
Mid-level analog/mixed-signal chip designer responsible for circuit design, layout, and verification of neural recording and stimulation SoCs. Requires 5+ years of CMOS circuit design experience in specialized areas like ADCs, DACs, or PLLs with proven silicon validation track record.

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Job description

from Neuralink careers

About Neuralink:

We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.

Team Description:

The Brain Interfaces SoC Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Job Description and Responsibilities:

The engineer will be responsible for analog and mixed-signal chip design, from circuit design to layout and verification. Other responsibilities include:

  • Design analog circuit building blocks and subsystems in transistor-level to achieve a variety of challenging noise, mismatch, distortion, power consumption, and cost requirements while satisfying top-level specifications
  • Works with layout teams to oversee block-level layout of multiple blocks
  • Planning and execution of analog verification plan for portion of IP or chip and runs complex simulations and analyses (e.g., power, performance, linearity, yield) on designs
  • Designs, programs, and runs complex tests and reviews tests of junior team members; ensures bugs and other issues are identified and appropriately analyzed
  • Consults with internal or external users and third-party vendors to guide implementation and ensure alignment with their needs and goals
  • This is an excerpt. Read the full job description on Neuralink careers →
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