Senior Design Verification Engineer
Micron · Jalisco, Mexico
About this role
Micron is hiring a senior-level Hardware Engineer in the software engineering function based in Jalisco, Mexico.
- Role
- Hardware Engineer
- Function
- software engineering
- Level
- senior
- Track
- Individual contributor
- Employment
- Full-time
- Location
- Jalisco, Mexico
- Posted
- Jun 2, 2026
More roles at Micron
Job description
from Micron careersOur vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
For more than 45 years, Micron Technology, Inc. has been at the forefront of innovation, delivering the world’s most advanced memory and semiconductor technologies. Our distributed team of engineers, scientists, and visionaries is developing groundbreaking solutions that redefine how the world uses information to enrich life for all.
Responsibilities:
Develop and implement verification strategies to ensure the robustness of HBM products.
Collaborate with develop, modeling, and architecture teams to implement advanced verification tools and methodologies.
Improve simulation flows and integrate digital and analog verification processes.
Support developing engineers and improve verification processes to achieve top-notch quality and efficiency.
Provide verification support by simulating, analyzing, and debugging pre-silicon full chip builds.
Minimum Qualifications:
Proficiency in establishing and simulating verification environments using Analog-Mixed Signal (Verilog+Spice).
Proficiency in Fastspice (Primesim/Finesim/Spectre) based simulation.
Proficient understanding of basic digital and analog circuits, simulation, troubleshooting, and evaluation.
Proven ability to guide and direct verification efforts within areas of expertise.
This is an excerpt. Read the full job description on Micron careers →