Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

As a Static Timing Analysis (STA) Engineer — you will be part of the Heterogeneous Integration Group (HIG), owning chip-level timing sign-off for next-generation die. You will work closely with RTL design, physical design, architecture, DFT, verification, and product teams to ensure timing integrity and drive timing closure across all modes and corners from initial design through tape-out.

This is a hands-on senior technical role focused on chip-level STA ownership, constraint authoring, timing closure, methodology development, and pre-/post-silicon timing correlation.

Key Responsibilities

Responsibilities will include, but are not limited to:
- Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, corners, and voltage and temperature conditions.
- Develop, maintain, and validate sign-off quality Synopsys Design Constraints (SDC) for clocks, resets, high-bandwidth memory (HBM) interfaces, design for test (DFT), and configuration logic.
- Drive timing closure at block, subsystem, and full-chip levels through critical path analysis, engineering change orders (ECOs), and close collaboration with physical design on placement, clock tree synthesis, and routing.

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SoC Timing (Static Timing Analysis/STA) Engineer, HBM

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Job description

Responsibilities will include, but are not limited to: