Design Verification Engineer
Intel · Folsom, CA
About this role
Intel is hiring a mid-level Hardware Engineer in the software engineering function based in Folsom, CA. The posting calls out experience with Testing. Compensation is listed at $141,910–$269,100 per year.
- Role
- Hardware Engineer
- Function
- software engineering
- Level
- mid
- Track
- Individual contributor
- Employment
- Full-time
- Location
- Folsom, CA
- Posted
- May 19, 2026
More roles at Intel
Job description
from Intel careersJob Description:
The Role and Impact
As an IP Design Verification Engineer, you will play a pivotal role in Intel's mission to advance cutting-edge technology. You will ensure that Intel's intellectual property (IP) designs meet rigorous quality standards, delivering robust and reliable solutions that power the innovations of tomorrow. In this role, you will collaborate with cross-functional teams to verify and validate complex architectural and microarchitectural features, contributing to Intel's industry leadership in hardware design and development. Your work will directly impact the performance, power efficiency, and reliability of next-generation computing systems, shaping the future of technology.
Key Responsibilities
- Develop and execute comprehensive IP verification plans to ensure compliance with microarchitecture specifications.
- Design, implement, and maintain test benches and verification environments to achieve optimal coverage.
- Define and run system simulation models to verify IP design functionality, analyze power and timing, and identify bugs.
- Debug, root cause, and resolve pre silicon design issues, implementing corrective measures for test failures.
- Collaborate with architects, RTL developers, and physical design teams to enhance the verification process for complex designs.
- Document verification plans and present technical reviews to design and architecture teams.
- Maintain and improve functional verification infrastructure, methodologies, and related workflows.
- Contribute to the definition and refinement of verification infrastructure and test framework methodologies (TFMs).