DFT Design Engineer

Job description

Job Description: 

DFx micro-Architecture :

• Drive technical readiness (TR), that is understand customer requirement and further design relevant DFT/DFD/DFV features. DFT stand for Design for testability (testability from tester), DFD stand for Design for debug (Debug capability in Silicon or customer end ) and DFV stand for Design for validation ( validate effective with simple flow and method )
• Architect and implement DFX strategy, These include provide uarch solution for TAP, Bscan, Scan, MBIST, IO DFX [ leakage, power, loopback ], debug port etc. for test testability and manufacturability.
• Define DFx design methodology and uarch to ensure good coverage [ Scan and functional ] for IP and meet products' DPM requirements
• Overseeing the Scan/ATPG definition, design, verification, and documentation
• Good and close loop communication across function group (Logic, Val, Ckt, SD, HVM ) to ensure a right DFX arch introduce to the IP.
• Perform yield analysis improvement and assisting the silicon debug
• Analyse product requirement to balance DFX requirements vs products' PPA and cost.

DFx RTL Design :

• Require RTL coding, pick up different RTL tool-based solution. Integrate all other DFx sub-IPs into one stop. Along process will require signal/clock connection, timing convergence and etc.
• Responsible to patch RTL logic for flawless area along execution phase. Ensure zero RTL design errors (bug free) as ultimate goal for DFx features.
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