Silicon Packaging Design Engineer
Intel · Penang, Malaysia
About this role
Intel is hiring a mid-level Hardware Engineer in the software engineering function based in Penang, Malaysia. The posting calls out experience with Performance Optimization.
- Role
- Hardware Engineer
- Function
- software engineering
- Level
- mid
- Track
- Individual contributor
- Employment
- Full-time
- Location
- Penang, Malaysia
- Posted
- Apr 20, 2026
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Job description
from Intel careersJob Description:
The Role and Impact:
Intel is seeking a motivated and innovative Layout Design Engineer to join our team of world-class semiconductor professionals. In this role, you will be at the forefront of designing the physical layout of of Intel's silicon that are used for its packaging technology. You will collaborate with customers, electrical engineers (for signal integrity and power delivery) to optimize performance, reliability, and manufacturability, driving innovation and efficiency across our cutting-edge products. As a Layout Design Engineer, you will play a critical role in ensuring Intel's continued leadership in the semiconductor industry, contributing to advanced methodologies and groundbreaking solutions.
Key Responsibilities:
Develop custom layouts for Intel's silicon used for its packaging technology.
Perform detailed physical array planning, area optimization, and signal and power routings.
Design and verify standard cell libraries, ensuring compliance with design rules, PDK specifications, and reliability requirements.
Execute layout verification processes, including checks for electron migration, voltage drop (IR), self-heat, ESD, and other reliability metrics.
Use custom auto-routers and placers to efficiently construct layouts and optimize designs.
Troubleshoot design, tool, and methodology issues related to layout construction.
Provide feedback to circuit design engineers on feasibility studies and implement circuit enhancement requests.
This is an excerpt. Read the full job description on Intel careers →