Senior Design Engineer – AI SoC Development
Intel · Folsom, CA
About this role
Intel is hiring a senior-level Security Analyst based in Folsom, CA. The posting calls out experience with Python, Security and roughly 7+ years of relevant work. Listed education preference: a bachelor's degree or equivalent. Compensation is listed at $190,610–$269,100 per year.
- Role
- Security Analyst
- Function
- security
- Level
- senior
- Track
- Individual contributor
- Employment
- Full-time
- Location
- Folsom, CA
- Experience
- 7+ years
- Education
- Bachelor's degree
- Posted
- May 19, 2026
More roles at Intel
Job description
from Intel careersJob Description:
About the Role Intel's AI SoC organization develops cutting-edge products powering a wide range of AI applications, from edge devices to data center accelerators. If you are an engineer with strong technical and communication skills who thrives in a fast-paced environment with abundant learning opportunities, you are the ideal candidate for this role. Join us to shape the future of AI hardware.
Position Overview You will develop logic design, register transfer level (RTL) coding, and simulation for SoC designs while integrating IP blocks and subsystems into full chip SoC or discrete component designs. You'll participate in defining architecture and microarchitecture features of the blocks being designed and perform quality checks across various logic design aspects ranging from RTL to timing/power convergence.
You will apply various strategies, tools, and methods to write RTL and optimize logic to meet power, performance, area, and timing goals while ensuring design integrity for physical implementation. Working closely with verification teams, you'll review verification plans and implementation to ensure design features are verified correctly, resolving and implementing corrective measures for failing RTL tests.
Additionally, you'll follow secure development practices to address security threat models and security objectives within the design, work with IP providers to integrate and validate IPs at the SoC level, and drive quality assurance compliance for smooth IP/SoC handoff.