Senior Silicon Test Engineer, ATE

Job description

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will develop and deploy comprehensive Automatic Test Equipment (ATE) solutions for high-volume manufacturing at Fabs and Outsourced Semiconductor Assembly and Tests (OSATs). You will integrate SoC technologies into devices and facilitate ATE testing to validate performance and screen units. You will lead all testing aspects, collaborating with cross-functional teams to ensure optimal production coverage and high-quality SoCs. You will need to have a strong background in IC flows, wafer processing, testing, and failure analysis. You will develop digital and mixed-signal tests, automation methodologies, and internal tools for test program management. You will be responsible for the end-to-end design, development, and validation of high-performance Integrated Circuit (IC) test interface hardware, including load boards, probe cards and socket change kits. Additionally, you will release cost-effective test solutions into mass production.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Design, implement, and manage IC product bring-up, verification, and characterization programs for NPI, including ATE test programs, load boards, and probe cards using ATE platforms such as UFLEX or 93K.
  
• Collaborate with vendors and internal teams to engineer high-volume ATE manufacturing solutions tailored for advanced packaging.
  
• Execute product and DPPM correlation between ATE and system-level environments for new products, and enhance test coverage and resolve varied failure modes via rigorous troubleshooting on ATE and System Level Test (SLT).
• Direct production sustaining activities, including program upgrades, yield optimization, test time reduction, lot disposition, and RMA analysis.
  
• Lead the architecture, schematic review, PCB layout supervision for high-density, multi-layer load boards and probe cards, and apply mechanical knowledge on design of custom socket, change kits and mechanical interface hardware, ensuring seamless integration between ATE and device under test.
  

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, a related degree, or equivalent practical experience.
• 8 years of experience in the semiconductor industry on ATE.
• Experience with IC testing, post-silicon enabling from new product introduction through high volume manufacturing, including experience in yield and Bin Pareto analysis.
• Experience with ATE hardware signal and power Integrity (SI/PI) analysis.
• Experience optimizing PDN target impedance and selecting appropriate decoupling capacitor strategies to minimize transient voltage noise and IR drop.
• Experience analyzing cross-talk, impedance discontinuities, insertion loss, return loss, and eye diagrams for high-speed interfaces (e.g., DDR, PCIe).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, a related degree, or equivalent practical experience.
• Experience with ATE platforms (Teradyne UltraFlex SOC and Advantest 93K) and knowledge of high-speed interfaces (DDR, PCIe, SERDES).
• Proven track record in semiconductor processing, VLSI product/test engineering, with SLT expertise using the Advantest platform.
  
• Proficiency in DFT methodologies, including memory BIST, JTAG, Scan/ATPG, and testing for PVT and temperature sensors.
  
• Competency in advanced packaging technologies such as InFO and 2.5D.
  
• Skilled in utilizing data analysis tools (O+, Datapower, or JMP).