Post Silicon Advanced Packaging Engineer
Google · Taipei, Taiwan | Zhubei, Taiwan
About this role
Google is hiring a mid-level Hardware Engineer in the software engineering function based in Taipei, Taiwan | Zhubei, Taiwan. The posting calls out experience with Python, Testing, GCP, Vertex AI and roughly 8+ years of relevant work. Listed education preference: a bachelor's degree or equivalent.
- Role
- Hardware Engineer
- Function
- software engineering
- Level
- mid
- Track
- Individual contributor
- Employment
- Full-time
- Location
- Taipei, Taiwan | Zhubei, Taiwan
- Experience
- 8+ years
- Education
- Bachelor's degree
- Posted
- Jun 29, 2026
Job description
from Google careersAs a Post Silicon Advanced Packaging Engineer, you will bridge the gap between post-silicon bring-up, foundry/OSAT manufacturing, and IC design. You will own the mass production yield, quality, and sustaining engineering for high-performance computing and AI products utilizing 2.5D/3D advanced packaging architectures. Your primary focus is maximizing package-level yield, resolving complex multi-die integration failures, and driving cross-functional engineering teams to optimize cost and reliability.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Responsibilities
- Monitor, analyze, and improve package-level yields for 2.5D/3D architectures. Track yield from known good die and interposer testing through final assembly and Class/System-Level Test.
- Identify and root-cause major yield detractors. Use statistical tools to correlate final package failures back to wafer-level testing, substrate defects, or assembly process variations.
- Act as the primary technical interface with foundries and OSATs. Drive suppliers on process control monitors, recipe optimizations, and corrective actions for assembly-induced defects.
- Characterize complex, multi-chip module failure mechanisms. Coordinate destructive and non-destructive Failure Analysis (FA) techniques.
- Feed post-silicon yield and FA learning back to the Design for Manufacturing and Design for Test teams to improve next-generation Chip-on-Wafer-on-Substrate (CoWoS)/Embedded Multi-die Interconnect Bridge (EMIB) product architectures.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience with product engineering and test engineering.
- Experience with 2.5D/3D packaging technologies, interposers, high-density substrates, and micro-bump metallurgical bonding.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience evaluating customer returns, identifying assembly issues and improvement plans.
- Experience in Python/Perl for data automation, statistical analysis, and yield management systems.
- Understanding of high bandwidth memory integration, die-to-die interfaces, and high-speed signal integrity challenges within a package.