CPU Performance Architect, Silicon
Google · New Taipei, Taiwan | Zhubei, Taiwan
About this role
Google is hiring a senior-level Hardware Engineer in the software engineering function based in New Taipei, Taiwan | Zhubei, Taiwan. The posting calls out experience with Python, C, Linux, Machine Learning and roughly 4+ years of relevant work. Listed education preference: a bachelor's degree or equivalent.
- Role
- Hardware Engineer
- Function
- software engineering
- Level
- senior
- Track
- Individual contributor
- Employment
- Full-time
- Location
- New Taipei, Taiwan | Zhubei, Taiwan
- Experience
- 4+ years
- Education
- Bachelor's degree
- Posted
- Jun 9, 2026
Job description
from Google careersAs a CPU Performance Architect, you will be the key contributor to improve processor instruction set architecture, to develop innovative microarchitecture features, and deliver Google’s advanced SoC products. You will collaborate cross-functionally with android applications and AI teams to conduct applications and benchmark performance analysis and to project their performance at various design phases. You will be guided by architects and work with engineers in Power, Thermal, Security, and Physical Design teams to determine the CPU subsystem configuration and features.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Develop and modify a performance model for performance analysis and microarchitecture study. Evaluate Advanced RISC Machine (ARM’s) architecture features from both architecture and performance angles.
- Define and write CPU subsystem architecture specifications.
- Collaborate with Register-Transfer Level (RTL), design verification, and physical design teams to develop a high-performance and efficient CPU implementation.
- Manage performance correlation between the performance model and RTL implementation, including micro-benchmark development and pre-silicon and post-silicon performance bug triage.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science, with a focus on computer architecture, or equivalent practical experience.
- 4 years of experience in microprocessor architecture, microarchitecture, performance, or advanced CPU design.
- Experience in CPU architecture, performance modeling, analysis, correlation, and workload characterization.
- Experience with C/C++ and scripting languages (e.g., Python).
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture or machine learning.
- Experience in CPU/ML microarchitecture exploration, performance model development, performance analysis, performance correlation, or workload characterization.
- Knowledge of microprocessor instruction set architecture (e.g., ARM, RISC-V, x86).
- Familiarity with system software components, such as Linux, drivers, and runtime.