senior machine learning Research Scientist ic 7+ yrs Phd's · Posted Jul 1, 2026
$174,000 – $253,000
USD per year

About this role

Google is hiring a senior-level Research Scientist in the machine learning function based in Goleta, CA | Cambridge, MA | Mountain View, CA | Seattle, WA | San Francisco, CA | Washington, DC. The role typically asks for 7+ years of relevant experience. Listed education preference: a Ph.D. or equivalent. Compensation is listed at $174,000–$253,000 per year.

Role
Research Scientist
Function
machine learning
Level
senior
Track
Individual contributor
Employment
Full-time
Location
Goleta, CA | Cambridge, MA | Mountain View, CA | Seattle, WA | San Francisco, CA | Washington, DC
Experience
7+ years
Education
Ph.D. preferred
Posted
Jul 1, 2026
AI Summary
Design and simulate superconductor digital logic circuits (SFQ, AQFP) for qubit control and readout. Collaborate with qubit designers using IC design tools, circuit simulation, and 3D electromagnetic modeling to optimize signal integrity and thermal management. Interface with fabrication engineers to establish cryogenic IC design standards for integrated quantum chip stacks.

Job description

from Google careers

As a Research Scientist, your primary focus will be designing and simulating superconductor digital logic circuits (such as single flux quantum (SFQ) logic and adiabatic quantum flux parametron (AQFP) logic) for qubit control and readout. You will engage in co-design loops with qubit designers and superconducting digital circuit designers, utilizing advanced IC design tools, numerical circuit simulation techniques and 3D electromagnetic modeling to optimize signal integrity, minimize crosstalk, manage thermal budgets, and aim performance metrics required for coherent control of qubits. You will also interface with fabrication engineers to help define and establish IC design standards that are compatible for both the sensitive superconducting qubits and the co-located cryogenic control electronics. This work is critical to building a fully integrated, modular chip stack that combines superconducting qubits with their control electronics directly within the cryogenic environment, accelerating the path toward large-scale, error-corrected quantum computer.

This work is critical to building a fully integrated, modular chip stack that combines superconducting qubits with their control electronics directly within the cryogenic environment, accelerating the path toward large-scale, error-corrected quantum computers.

The full potential of quantum computing will be unlocked with a large-scale computer capable of complex, error-corrected computations. Google Quantum AI's mission is to build this computer and unlock solutions to classically intractable problems. Our roadmap is focused on advancing the capabilities of quantum computing and enabling meaningful applications.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $174000 - $253000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

  • Design and simulate superconductor digital logic circuits (such as single flux quantum (SFQ) logic, adiabatic quantum flux parametron (AQFP) logic, and other emerging superconductor logic families) for generating waveforms tailored to qubit control and readout.
  • Develop superconductor digital logic systems enabling multiplexed qubit control and readout.
  • Address issues in the integration of superconductor digital electronics such as multi-layer cell design, full-chip clock synchronization, flux trapping, and signal integrity.
  • Collaborate with teams focused on design, fabrication, and measurement to validate fully integrated quantum processors.
  • Publish research papers and present at leading scientific conferences to advance and enhance publicity.

Minimum qualifications:

  • Master's degree in Electrical Engineering, Physics, related engineering discipline, or equivalent practical experience.
  • Experience in superconductor logic families (e.g., RSFQ, ERSFQ, RQL, HFQ, AQFP).
  • Experience performing tape-out of a superconducting IC chip.
  • One or more published research paper or presentation at a relevant scientific conference.

Preferred qualifications:

  • PhD in physics, electrical engineering, or a related engineering discipline.
  • 7 years of research/industry experience in the design and simulation of superconductor digital logic circuits with 3 years of experience leading an Research and Development (R&D) group towards tape-out and demonstration of superconducting IC chips.
  • Experience with full digital design flow including RTL, synthesis, verification, timing closure, place-and-route, and post-fabrication validation.
  • Experience with low-temperature measurements of superconductor digital logic circuits.
  • Experience with superconducting qubits.
  • Proficiency with computer-aided design tools and electromagnetic simulation tools.

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