ASIC DFT CAD Technical Leader
Cisco · San Jose, CA · Product and Engineering
About this role
Cisco is hiring a senior-level Hardware Engineer in the software engineering function based in San Jose, CA. The posting calls out experience with Python, Bash, pandas, Testing. Compensation is listed at $183,800–$263,600 per year.
- Role
- Hardware Engineer
- Function
- software engineering
- Level
- senior
- Track
- Individual contributor
- Employment
- Full-time
- Location
- San Jose, CA
- Department
- Product and Engineering
- Posted
- May 5, 2026
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Job description
from Cisco careersJob posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
Who We Are:
The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world.
Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's revolutionary solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.
Key Responsibilities:
Own and drive end-to-end DFT flow architecture.
Build and maintain scalable DFT CAD infrastructure from RTL ‚ DFT insertion, ATPG, simulation, reporting.
Develop robust regression frameworks (LSF/cluster-based) with job orchestration, monitoring, logging, and failure recovery.
Lead AI-driven automation initiatives for log analysis, failure triage, regression optimization, and intelligent debug.
This is an excerpt. Read the full job description on Cisco careers →