ASIC High Speed AMS Technical Leader
Cisco · Carlsbad, CA · Product and Engineering
About this role
Cisco is hiring a principal-level Principal Engineer in the software engineering function based in Carlsbad, CA. The posting calls out experience with Python, C, Serverless, Testing. Compensation is listed at $189,300–$271,500 per year.
- Role
- Principal Engineer
- Function
- software engineering
- Level
- principal
- Track
- Tech leadership
- Employment
- Full-time
- Location
- Carlsbad, CA
- Department
- Product and Engineering
- Posted
- May 5, 2026
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Job description
from Cisco careersJob posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
Meet the Team
Cisco’s Client Optics Group (COG) designs & delivers the high-speed optical transceivers, and platforms that power Cisco's core data center networking solutions. We specialize in the design and integration of innovative IM/DD optics and silicon photonic platforms that enable customers to deploy industry-leading optical technologies within data center with unprecedented speed, capacity, and reliability. Come join us and take part in shaping COG’s ground-breaking optical solutions by designing, developing, and testing some of the most advanced pluggable, and Co-packaged Optics (CPO) being developed in the industry.
You will work with Cisco's best-in-class Silicon Photonics team. Our team is responsible for driving the development and optimization of optical transceivers & modules (800G,1.6T & beyond) that seamlessly integrate with Cisco's routing, switching, and datacenter platforms, enabling customers to build scalable, high-performance networks that support emerging technologies including AI/ML workloads, and next-generation data center architectures.
We are seeking an experienced High Speed AMS Design Engineer to lead full-chip electrical specifications and mixed-signal design for Cisco's silicon photonics driver integrated circuits supporting 100G/200G/400G per Lambda solutions. You will own high-speed datapath and low-speed control circuit design for receive and transmit paths in our next-generation silicon photonics modules.