Senior ASIC Physical Design CAD Engineer
Cisco · Caesarea, Israel · Product and Engineering
About this role
Cisco is hiring a senior-level Hardware Engineer in the software engineering function based in Caesarea, Israel. The posting calls out experience with Backend Development and roughly 5+ years of relevant work. Listed education preference: a bachelor's degree or equivalent.
- Role
- Hardware Engineer
- Function
- software engineering
- Level
- senior
- Track
- Individual contributor
- Employment
- Full-time
- Location
- Caesarea, Israel
- Experience
- 5+ years
- Education
- Bachelor's degree
- Department
- Product and Engineering
- Posted
- May 6, 2026
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Job description
from Cisco careersSilicon One is seeking a CAD Engineer to join the Cisco Silicon One Physical Design team.
Meet the Team
You'll be part of the Cisco Silicon One team, which is at the heart of Cisco’s software and ASIC design efforts.
As part of our team, you’ll contribute to the development of our next-generation network devices—Cisco Silicon One™. Our team operates in a startup-like environment within a stable and leading corporation.
Our design center is uniquely equipped, hosting all silicon hardware and software development fields under one roof.
We are revolutionizing the industry by building a new internet for the 5G era, providing a unified, programmable silicon architecture that serves as the foundation for all of Cisco's future routing products. Our devices are designed to be universally adaptable across service providers and web-scale markets, catering to both fixed and modular platforms. They deliver high speed without compromising on programmability, buffering, power efficiency, scale, or feature flexibility.
Cisco Silicon One is a ground-breaking, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, and safer engine!
Your Impact
You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.