About this role

Cadence Design Systems is hiring a senior-level Software Engineer based in Shanghai, China. The posting calls out experience with C, C++ and roughly 3–5 years of relevant work. Listed education preference: a bachelor's degree or equivalent.

Role: Software Engineer
Function: software engineering
Level: senior
Track: Individual contributor
Employment: Full-time
Location: Shanghai, China
Experience: 3–5 years
Education: Bachelor's degree
Posted: Jul 8, 2026

AI Summary

Develop and maintain the Palladium synthesizer, implementing new VHDL/Verilog features, optimizing logic, and improving performance. Requires Bachelor's or Master's in EE/CS/CE with C/C++ proficiency, RTL modeling expertise, and EDA/CAD tool development experience preferred.

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Job description

from Cadence Design Systems careers

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Description:

Responsible for development and maintenance of the synthesizer for Palladium.
Implementation for new VHDL/Verilog feature support in synthesizer.
Logic optimization and performance improvement in synthesizer.

Position Requirement:

This position requires a Bachelor or Master's degree in EE/CS/CE with 3-5 years of industry experience.
Candidate should be proficient with C/C++, Operating system concepts.
Design modeling using Verilog/SV, VHDL or SysC.
Knowledge and experience in RTL modeling of BFMs along with exposure to verification methodologies using UVM and SC/TLM is preferable.
EDA/CAD tool development experience or logic design verification experience is highly preferred.
Knowledge and experience in AI tools like Copilot or Claude code is preferred.
Requires good communication skills, attention to details, and ability to work in multi-site/multi-person project.