Software Engineer ll - Timing Analysis
Cadence Design Systems · San Jose, CA
About this role
Cadence Design Systems is hiring a mid-level Software Engineer based in San Jose, CA. The posting calls out experience with Data Structures, Machine Learning. Compensation is listed at $101,500–$188,500 per year.
- Role
- Software Engineer
- Function
- software engineering
- Level
- mid
- Track
- Individual contributor
- Employment
- Full-time
- Location
- San Jose, CA
- Posted
- May 8, 2026
More roles at Cadence Design Systems
Job description
from Cadence Design Systems careersAt Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We are searching for a Software Engineer to work on delay calculation and signal integrity (SI) analysis in Static Timing Analysis tool. Responsible for implementing and extending existing capabilities for circuit and interconnect delay and signal integrity analysis of large scale circuits, investigating techniques to improve correlation of delay/SI analysis to SPICE, and modeling of nanometer circuit effects in delay/SI analysis.
The role involves designing, tuning, and innovating timing and graph algorithms operating on multi‑billion‑node timing graphs. These scale challenges require highly distributed, incremental, and parallel solutions, including opportunities to leverage GPU acceleration for performance‑critical workloads.
At advanced technology nodes, incorporating device variation and statistical modeling into the timing engine introduces additional complexity.
Position Requirements:
The candidate should have MS/PhD in EE/CS or related discipline, strong programming skills in C++, and deep familiarity with object-oriented programming methods. Prior knowledge and experience with multi-threaded programming, numerical analysis techniques, and delay calculation methods for nanometer circuits preferred.