Applied ML – Functional Verification Engineer
Cadence Design Systems · San Jose, CA
mid
Machine Learning Engineer
ic
2+ yrs Bachelor's
· Posted Apr 20, 2026
$114,800 – $213,200
USD per year
About this role
Cadence Design Systems is hiring a mid-level Machine Learning Engineer based in San Jose, CA. The posting calls out experience with LLMs, RAG, Reinforcement Learning, Machine Learning and roughly 2+ years of relevant work. Listed education preference: a bachelor's degree or equivalent. Compensation is listed at $114,800–$213,200 per year.
- Role
- Machine Learning Engineer
- Function
- machine learning
- Level
- mid
- Track
- Individual contributor
- Employment
- Full-time
- Location
- San Jose, CA
- Experience
- 2+ years
- Education
- Bachelor's degree
- Posted
- Apr 20, 2026
AI Summary
Mid-level ML engineer developing AI-powered chip verification solutions using LLMs and agentic AI. Applies machine learning to streamline pre-silicon verification methodologies like formal verification and UVM. Collaborates with ML and software teams to validate correctness and deploy next-generation EDA tools.
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Job description
from Cadence Design Systems careersAt Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Position Overview
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