Senior Principal Software Engineer - Accelerated Verification IP
Cadence Design Systems · San Jose, CA
About this role
Cadence Design Systems is hiring a senior-level Software Engineer based in San Jose, CA. The posting calls out experience with C++, C, Performance Optimization. Compensation is listed at $154,000–$286,000 per year.
- Role
- Software Engineer
- Function
- software engineering
- Level
- senior
- Track
- Tech leadership
- Employment
- Full-time
- Location
- San Jose, CA
- Posted
- Apr 20, 2026
More roles at Cadence Design Systems
Job description
from Cadence Design Systems careersAt Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The AVIP (Accelerated Verification IP) and Virtual Bridge (VB) business is a core part of Cadence’s Virtual Emulation and System Verification portfolio, enabling high‑performance verification on Palladium and Protium platforms. The team builds high‑performance protocol solutions that enable customers to verify complex SoCs and systems at much higher speed and scale than traditional simulation.
Together, AVIP and VB are critical to customers building high‑performance compute, AI, networking, and memory‑coherent systems, where early software bring‑up, performance analysis, and protocol compliance are essential.
The AVIP / Virtual Bridge R&D team designs, implements, and productizes protocol solutions that span hardware, software, and system‑level verification. The team works across multiple layers, including:
- Protocol architecture and feature definition
- High‑performance transactor and BFM development
- Hardware‑software co‑simulation and emulation flows
- Debug, logging, performance profiling, and compliance features
- Customer enablement, escalations, and interoperability validation
The team supports a broad portfolio of industry‑standard protocols, such as PCIe, CXL, Ethernet, USB, UCIe, and emerging interconnects, and works closely with emulation platform teams, controller/PHY teams, and customers.
This role will contribute directly to the development and enhancement of PCIe/CXL AVIP and/or PCIe/CXL Virtual Bridge products, focusing on protocol functionality, performance, and robustness. Depending on the specific protocol area, the work may involve: