Design Verification Lead Engineer
Cadence Design Systems · Austin, TX
senior
software engineering
Hardware Engineer
ic
5+ yrs Bachelor's
· Posted Apr 20, 2026
About this role
Cadence Design Systems is hiring a senior-level Hardware Engineer in the software engineering function based in Austin, TX. The posting calls out experience with Python, CI/CD, Testing and roughly 5+ years of relevant work. Listed education preference: a bachelor's degree or equivalent.
- Role
- Hardware Engineer
- Function
- software engineering
- Level
- senior
- Track
- Individual contributor
- Employment
- Full-time
- Location
- Austin, TX
- Experience
- 5+ years
- Education
- Bachelor's degree
- Posted
- Apr 20, 2026
AI Summary
Lead design verification engineer managing test coverage and closure for CPU cores using UVM, SystemVerilog, and automated regression environments. Requires 5+ years VLSI verification experience, strong SVA and constraint randomization skills, processor integration knowledge (RISC-V/ARM), and scripting expertise.
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Job description
from Cadence Design Systems careersAt Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Design Verification Lead Engineer
Role Overview:
The Lead DV Engineer focuses on the execution and technical management of verification projects. You will lead a focused team to ensure comprehensive test coverage and closure for specific CPU cores or processor blocks.
Key Responsibilities:
- Technical Execution: Developing and executing detailed verification plans (vPlans) using Cadence vManager.
- Environment Development: Develop UVM scoreboards, monitors, and complex functional coverage models for multi-protocol or processor-specific interfaces.
- Debug & Triage: Lead the debug of complex RTL failures and coordinate with design engineers to resolve microarchitectural bugs.
- Regression Management: Manage automated regression environments (e.g., Jenkins) and ensure targets for code and functional coverage are met.
- Project Tracking: Responsible for technical alignment, project planning, and progress tracking for the verification lifecycle.
Required Qualifications:
- B.S/M.S in EEE with 5–8+ years of hands-on experience in VLSI design verification.
- Strong command of SystemVerilog Assertions (SVA), constraint randomization, and UVM.
- Experience with processor integration (e.g., RISC-V or ARM) and industry-standard protocols like AMBA/PCIe.
- Expertise in scripting (Perl, Python, or Tcl) for verification flow automation.
We’re doing work that matters. Help us solve what others can’t.
This is an excerpt. Read the full job description on Cadence Design Systems careers →