Lead Design Engineer
Cadence Design Systems · Pune, India
About this role
Cadence Design Systems is hiring a senior-level Systems Engineer in the operations function based in Pune, India. The posting calls out experience with Python, C, Linux, Testing and roughly 4+ years of relevant work. Listed education preference: a bachelor's degree or equivalent.
- Role
- Systems Engineer
- Function
- operations
- Level
- senior
- Track
- Individual contributor
- Employment
- Full-time
- Location
- Pune, India
- Experience
- 4+ years
- Education
- Bachelor's degree
- Posted
- Apr 20, 2026
More roles at Cadence Design Systems
Job description
from Cadence Design Systems careersAt Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence Tensilica CPU/DSP Processor Team is hiring senior engineers to join our R&D teams in Pune, Bangalore and Noida. This is an amazing opportunity to work in an impactful job at a world leader in computational software, semiconductor design IP, and system verification hardware. Come be part of this great Processor team where you can make an impact that is visible.
Lead Engineer positions are for one of the two roles:
(a) Perform as a member of the Logic Design Team for Xtensa processors. Responsible for the RTL implementation of microprocessor cores, multiprocessor sub-systems and their peripherals. Implement the micro-architecture in Verilog RTL, simulate and debug its functions and run synthesis, place & route and other Electronic Design Automation scripts to meet timing, area, and power goals. Assist with developing test plans; writing functional diagnostics; debugging failures; and analyzing coverage information. Work closely with various Design Verification and Electronic Design Automation teams.
(b) Perform as a member of the Design Verification Team for Xtensa processors. Responsible for verification of microprocessor cores, multiprocessor sub-systems and their peripherals. Assist with developing test plans, writing functional assembly diagnostics, UVM/SVA monitors, debugging failures, and analyzing coverage information. Work closely with various RTL Design and Electronic Design Automation teams.