Principal Design Engineer

Cadence Design Systems · Pune, India

principal operations Systems Engineer tech_leadership 8-10 yrs Bachelor's · Posted Apr 20, 2026
Skills
C Linux

About this role

Cadence Design Systems is hiring a principal-level Systems Engineer in the operations function based in Pune, India. The posting calls out experience with C, Linux and roughly 8–10 years of relevant work. Listed education preference: a bachelor's degree or equivalent.

Role
Systems Engineer
Function
operations
Level
principal
Track
Tech leadership
Employment
Full-time
Location
Pune, India
Experience
8–10 years
Education
Bachelor's degree
Posted
Apr 20, 2026
AI Summary
Principal-level Systems Engineer developing and verifying hardware and software safety mechanisms for Xtensa processors. Leads functional safety design verification through simulation, diagnostics, and fault analysis. Requires 8-10 years design verification experience, team leadership, strong computer architecture knowledge, Verilog/SystemVerilog expertise, and ISO 26262 safety standards proficiency.
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Job description

from Cadence Design Systems careers

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence IP Tensilica group  is a leading provider of configurable embedded processor technology, with a growing presence in the Automotive Safety market. As a member of the Functional Safety Design Verification Team for Xtensa processors you will be responsible for development and verification of hardware and software safety mechanisms. You will implement simulation or emulation test benches, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target safety and product verification goals. You will also assist with fault simulation and analyzing coverage information. You will work closely with the RTL, EDA, and Functional Safety teams. You will develop and deliver functional safety work products, including documentation needed for product safety certification.

Required Skills and Experience: 

  • 8-10 years of design verification experience
  • BS (or higher) in EE/Computer Engineering
  • Experience in leading a small team
  • Excellent knowledge of computer architecture/micro-architecture and design verification fundamentals
  • Expertise with Verilog and popular EDA simulation, SystemVerilog assertions and functional coverage
  • Good working knowledge of scripting languages like Perl, Unix shell or similar languages
  • Knowledge of technical safety concepts and requirement specifications according to ISO 26262
    • This is an excerpt. Read the full job description on Cadence Design Systems careers →
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