mid software engineering Hardware Engineer ic 10+ yrs Bachelor's · Posted Jun 12, 2026

Skills

About this role

Apple is hiring a mid-level Hardware Engineer in the software engineering function based in Beaverton, OR. The posting calls out experience with Python and roughly 10+ years of relevant work. Listed education preference: a bachelor's degree or equivalent.

Role: Hardware Engineer
Function: software engineering
Level: mid
Track: Individual contributor
Location: Beaverton, OR
Experience: 10+ years
Education: Bachelor's degree
Department: Hardware
Posted: Jun 12, 2026

AI Summary

Drive CPU block-level power delivery verification and implementation for Apple Silicon, including EMIR/electrical closure, power grid design, and multi-functional collaboration. Requires 10+ years silicon power delivery experience with SAPR/EMIR automation scripting and deep sub-micron technology expertise.

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Job description

from Apple careers

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products!

Apple’s Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level implementation.
• Drive block and top-level EMIR/electrical verification closure
• Work on power grid design, construction, and implementation using existing infrastructures and where necessary, creating custom solutions in PNR tool environment
• Work multi-functionally with CAD/EDA vendors to ensure fidelity of analysis results with methodology teams to cover unique use cases, with implementation teams to drive design and sign-off closure, and with the SOC level teams to meet IP delivery quality and schedule
<h3>Minimum Qualifications</h3>Minimum BS and 10+ years of relevant industry experience
Experience with silicon level power delivery, electromigration, and IR drop analysis
Experience with scripting of SAPR or EMIR flow automation for the efficient processing of large scale design and analysis data, debugging of issues, and isolating design sensitivities
<h3>Preferred Qualifications</h3>Experience implementing high-performance and low-power VLSI designs
Experience with SAPR/PNR design flow infrastructure
Understanding of challenges related to latest deep sub-micron technology
Produce impactful design fixes and automate wherever possible, spanning multiple tool domains in physical construction and analysis
Working knowledge of industry standard tools like Apache Redhawk and Cadence Voltus as well as PNR implementation, layout tools, verification, and STA
Strong communication and presentation skills to regularly summarize the state of the design and drive design convergence across multiple blocks and teams in a timely fashion