SoC Physical Design Engineer, STA/Timing
Apple · Waltham, MA · Hardware
About this role
Apple is hiring a mid-level Hardware Engineer in the software engineering function based in Waltham, MA. The posting calls out experience with Python and roughly 10+ years of relevant work. Listed education preference: a bachelor's degree or equivalent.
- Role
- Hardware Engineer
- Function
- software engineering
- Level
- mid
- Track
- Individual contributor
- Location
- Waltham, MA
- Experience
- 10+ years
- Education
- Bachelor's degree
- Department
- Hardware
- Posted
- Jun 10, 2026
Job description
from Apple careersImagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it! Join us to help deliver the next groundbreaking Apple product.
In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC using state of the art process technology.
- Work with design teams to understand and debug constraints and facilitate logic changes to improve timing.
- Work with the Physical Design team, highlighting issues and best practices.
- Help create timing ECO’s for project tapeout.
- Create and maintain scripts and methodologies for analysis and runs.
- Create documentation and help with guidelines/specs.
- Deep analysis of timing paths to identify key issues.
- Implement timing infrastructure.
<h3>Minimum Qualifications</h3>Minimum BS and 10+ years of relevant industry experience
Strong programming skills with TCL
<h3>Preferred Qualifications</h3>Experience with large design STA and/or Timing Closure.
Experience with timing of large high-performance SoC designs in sub-micron technologies.
Deep understanding of noise, crosstalk, OCV and other timing modeling effects.
Knowledge of circuit modeling including timing models, worst-case timing corner selection, and SPICE simulation.
Experience in ECO techniques and implementation.
Experience with other scripting languages such as Perl or python.
Good communicator who can accurately describe issues, propose solutions, and drive them through completion.