SoC Power Analysis and Optimization Engineer
Apple · Cupertino, CA · Hardware
About this role
Apple is hiring a mid-level Security Analyst based in Cupertino, CA. The posting calls out experience with Python, Data Structures, Machine Learning. Listed education preference: a bachelor's degree or equivalent.
- Role
- Security Analyst
- Function
- security
- Level
- mid
- Track
- Individual contributor
- Location
- Cupertino, CA
- Education
- Bachelor's degree
- Department
- Hardware
- Posted
- Apr 10, 2026
Job description
from Apple careersAs part of our Silicon Engineering group, you will take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. Join us, and you will help design products that bring to our customers experiences they’ve never before envisioned. In this highly visible role, you will be responsible for SOC power optimization automation, power modeling, and simulation.
The main responsibility of this role is to drive the automation for SOC power optimization.
- Working with SOC power team members to automate the power analysis and optimization tasks
- Explore new methodology to analyze the power data, create power metrics to identify the optimization opportunities, drive automated approach to improve SOC power efficiency across IPs
- Explore machine learning approaches to optimize SOC power, work with team members on training data preparation, research ML based solution for power simulation, optimization and modeling.
- Collaborate cross-functional teams to deploy the power optimization automation to improve SOC power, review results, improve the methodology on efficiency, runtime, and support boarder scope of designs.
<h3>Minimum Qualifications</h3>A minimum of a bachelor's degree in related field
<h3>Preferred Qualifications</h3>MSEE preferred
Familiarity with machine learning algorithms and programming
Familiarity with scripting in Python.
Familiarity with ASIC power analysis and optimization
Familiarity with SOC design flow and methodology
Familiarity with Verilog and System Verilog.
Familiarity computer architecture, logic and circuits design
Familiarity signal processing is a plus
Silicon power measurement experience is a plus
SOC power modeling, low power design and power optimization experience is a plus
Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups