About this role

Apple is hiring a mid-level Data Engineer based in Santa Clara, CA. The posting calls out experience with Python, Testing. Listed education preference: a bachelor's degree or equivalent.

Role: Data Engineer
Function: data engineering
Level: mid
Track: Individual contributor
Location: Santa Clara, CA
Education: Bachelor's degree
Department: Hardware
Posted: Apr 9, 2026

AI Summary

Mid-level Data Engineer integrating IP blocks and RTL codebases into SoCs, managing design constraints, timing closure, and build infrastructure. Requires bachelor's degree and expertise in ASIC design flows, SystemVerilog/Verilog, SoC tools (Synopsys, Cadence), and bus protocols (AXI, AHB, APB).

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Job description

from Apple careers

Imagine what you could do here. At Apple, new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Sophisticated, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. Join us to help deliver the next excellent Apple product.

Do you enjoy working on challenges that no one has solved yet? As a member of our complex group, you will get the outstanding and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a dedicated engineer to join our exciting team of problem solvers.
The ideal candidate will have experience in ASIC design with:
• IP Integration: Integrate third-party or internal IP blocks (e.g., CPU, GPU, memory controllers, custom logic) into a SoC.
• RTL Integration: Manage and merge RTL codebases, ensure connectivity and bus/interface protocols (e.g., AMBA, AXI, AHB) are correctly implemented.
• Top-Level Assembly: Create and maintain top-level SoC RTL, wrappers, and interconnects.
• Linting and Synthesis: Run and debug lint, CDC/RDC, and logic synthesis to ensure design quality.
• Build and Test Infrastructure: Develop and maintain automated build and regression systems for integration.
• Design Constraints: Define and validate synthesis and timing constraints (SDC files).
• Timing Closure: Work closely with physical design and STA teams to achieve timing closure at top level.
• Functional Verification Support: Provide integration-level support to design verification teams, including simulation bring-up and debug.
• Documentation and Reviews: Create and maintain design documents and participate in design reviews.
<h3>Minimum Qualifications</h3>Bachelor's Degree with +0 Years of Experience
<h3>Preferred Qualifications</h3>Solid understanding of digital logic design and RTL development (SystemVerilog, Verilog).
Familiarity with SoC design flows and tools (e.g., Synopsys, Cadence).
Experience with bus protocols (AXI, AHB, APB) and interface standards (PCIe, USB, DDR).
Knowledge of ASIC tool flows: lint, synthesis, CDC, DFT, STA.
Strong scripting skills (Python, Perl, TCL, Shell) for automation.
Good debugging and problem-solving skills.
Excellent communication and cross-functional collaboration.