DFT Engineer

Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE: 

We are seeking a motivated DFx engineer to join our SOC design team. In this role, you will contribute to the next generation of AMD’s silicon innovation while developing your expertise in DFx methodologies and advanced design practices. You will be part of a forward‑thinking engineering organization that values learning, encourages fresh ideas, and empowers emerging talent to grow into impactful contributors who help shape the future of semiconductor technology

THE PERSON:  

You have a passion for modern and advanced DFx design and techniques. You are a team player with excellent communication skills and experience collaborating with engineers located across different sites and time zones. You have strong analytical and problem‑solving skills, are willing to learn, and are ready to take on challenges.

KEY RESPONSIBILITIES:  

• Implement and verify DFT features such as SCAN, MBIST, and BSCAN.
• Perform Spyglass DFT bring-up, debug and coverage improvement.
• Perform scan insertion and ATPG (Traditional, Cell Aware, SSN) pattern generation.
• Verify ATPG patterns using gate level simulation.
• Analyze and improve ATPG and DFT DV test coverage.
• Develop and debug DFT verification tests.
• Work with the Synthesis and PD team to ensure correct DFT implementation and timing closure.
• Provide post silicon support to ensure successful bring up.

PREFERRED EXPERIENCE:  

• Experience in scan stitching and strong knowledge of scan stitching concepts.
• Exposure to MBIST/BISR implementation and the Synopsys SMS MBIST insertion flow.
• Excellent hands on ATPG experience and familiarity with ATPG related file requirements.
• Knowledge or experience with Tessent SSN (Siemens) is a plus.
• Knowledge of Spyglass DFT.
• Good in C++ and object-oriented programming concepts.
• Familiarity with automation scripts such as Perl or Python is a plus.
• Understanding of JTAG and IJTAG fundamentals.
• Exposure to AI related work is a plus.
• Experience with post silicon bring up is a plus.
• Exposure to static timing analysis and timing closure is a plus

ACADEMIC CREDENTIALS:  

• Bachelors or Masters degree in computer engineering/Electrical Engineering.

LOCATION:

Penang, Malaysia

RTG

#LI-JL1

#LI-Hybrid

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.