ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs
Amazon · Cupertino, CA · Software Development
About this role
Amazon is hiring a senior-level Hardware Engineer in the software engineering function based in Cupertino, CA. The posting calls out experience with Python, AWS, Data Structures, Machine Learning. Compensation is listed at $157,300–$212,800 per year.
- Role
- Hardware Engineer
- Function
- software engineering
- Level
- senior
- Track
- Individual contributor
- Employment
- Full-time
- Location
- Cupertino, CA
- Department
- Software Development
- Posted
- Feb 27, 2026
More roles at Amazon
Job description
from Amazon careersAmazon Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world. We have data center locations in the U.S., Europe, Singapore, and Japan, and customers across all industries. Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Our success depends on our world-class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies. We’re looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs. Key job responsibilities As an ASIC Design Engineer, you will: • Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets • Conduct in-depth analysis of designs, microarchitectures, and architectures to optimize trade-offs between features, power consumption, performance, and area requirements • Create microarchitectures, implement SystemVerilog RTL, and deliver synthesis and timing-clean designs with appropriate constraints • Execute lint…