ASIC Design Verification Engineer
Qualcomm · Markham
About this role
Qualcomm is hiring a mid-level Hardware Engineer in the software engineering function based in Markham. The posting calls out experience with Python, TensorFlow, PyTorch, scikit-learn. Compensation is listed at $90,100–$135,100 per year.
- Role
- Hardware Engineer
- Function
- software engineering
- Level
- mid
- Track
- Individual contributor
- Location
- Markham
- Posted
- May 15, 2026
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Job description
from Qualcomm careers##
Company:
Qualcomm Canada ULC
## Job Area:
Engineering Group, Engineering Group > ASICS Engineering
General Summary:
Qualcomm-Atheros is a leading provider of wireless and wired technologies for the mobile, networking, computing and consumer electronics markets. We're focused on inventing technologies that connect and empower people in ways that are elegant and accessible to all. Qualcomm Atheros' teams deliver cutting-edge products across every established wireless standard/protocol.
We are currently seeking candidates for positions involving the implementation of optimum system architectures, interfaces and logics for connectivity RF/Analog system. Successful candidates will be responsible for participating in development of leading-edge ASICs for multi-function mobile platforms. Candidates will work with engineers or develop unit-level and integrated-level test benches. Candidate will assist in synthesis and gate-level simulation tasks related to your module and will assist with timing of the entire chip. Candidate will leverage knowledge of wireless LAN, Bluetooth, and RF transceiver.
New Position
Ideal candidate will have:
*RTL Design
*ASIC front-end experience
*Scripting Languages knowledge (e.g. Perl or Python)
## Responsibilities:
* Develop and debug behavioral models for event-driven and mixed-signal simulation based on analog circuit design.
* Create verification plans for radio and IP modules interfacing with SoC.
* Build self-checking test benches and define test coverages and sequences.