AI Architecture & Governance Leader Enterprise AI Platforms
Qualcomm · San Diego, CA
About this role
Qualcomm is hiring a director-level AI Infrastructure Engineer in the machine learning function based in San Diego, CA. The posting calls out experience with AWS, GCP, Azure, Kubernetes. Compensation is listed at $192,600–$289,000 per year.
- Role
- AI Infrastructure Engineer
- Function
- machine learning
- Level
- director
- Track
- Individual contributor
- Location
- San Diego, CA
- Posted
- Mar 16, 2026
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Job description
from Qualcomm careers##
Company:
Qualcomm Incorporated
## Job Area:
Engineering Group, Engineering Group > Software Engineering
General Summary:
Drive the design, governance, and responsible adoption of AI across the enterprise. In this role, you’ll establish a collaborative governance ecosystem spanning models, datasets, fine‑tuned adapters, prompts, agents, AI products, and implementations—while partnering closely with Enterprise Architecture to define high‑level patterns and reference architectures. You’ll guide the prioritization of use cases, shape the enterprise AI platform strategy (cloud and on‑prem), and ensure AI solutions are secure, scalable, cost‑efficient, and compliant. If you thrive at the intersection of architecture, governance, and product leadership—and you’re excited to unlock value from agentic automation—this is for you.
This role requires full-time onsite work in San Diego, CA (5 days per week).
Key Responsibilities
Architecture & Platform
* Define end‑to‑end AI solution architectures (cloud & on‑prem) including model serving, RAG/LLM patterns, vector indexing, data integration, and observability.
* Establish reference architectures, “golden paths,” and reusable templates that integrate with the enterprise AI platform.
* Lead evaluations and POCs of AI capabilities (LLM serving engines, vector DBs, orchestration frameworks, evaluation toolchains, guardrails).
* Partner with Enterprise Architecture to align AI patterns with enterprise standards, security, and roadmaps.
* Guide the design of scalable inference topologies (GPU/CPU, autoscaling, caching, batching, token optimization) and performance tuning.