Senior ASIC Verification Engineer - Hardware
Nvidia · Shanghai, China
About this role
Nvidia is hiring a senior-level Hardware Engineer in the software engineering function based in Shanghai, China (hybrid). The posting calls out experience with Python, C, Frontend Development and roughly 5+ years of relevant work. Listed education preference: a bachelor's degree or equivalent.
- Role
- Hardware Engineer
- Function
- software engineering
- Level
- senior
- Track
- Individual contributor
- Employment
- Full-time
- Location
- Shanghai, China
- Work mode
- Hybrid
- Experience
- 5+ years
- Education
- Bachelor's degree
- Posted
- Apr 20, 2026
More roles at Nvidia
Job description
from Nvidia careersNVIDIA SOC System-ASIC team is hiring a verification engineer. In this role, you will work closely with Arch, design and verification engineers to thoroughly verify some top-level related control units (like: Fuse/Floorsweep, Strap, Reset, Sysctrl) and some silicon measurement related units from unit-level to fullchip-level. Those units are important IPs used in both NVIDIA GPU and Tegra products.
What you’ll be doing:
Micro-architecture definition for System-level modules (Fuse, Strap, Floorsweep, In-silicon measurement, Reset, Sysctrl, etc...)
Unit-level and System-level verification for System-level modules.
Own some NVIDIA internal checks to guarantee the design quality.
What we need to see:
BS / MS or equivalent experience in electrical / computer engineering and related.
Above 5 years of ASIC design/verification experience.
Familiar with verification methodology, tools and flow.
Understand frontend ASIC design flow including RTL design, synthesis and timing analysis.
Excellent analytical and problem-solving skills.
Fluent English (both written and spoken) and excellent communication skills.
Good team work spirit, easy to cooperate with team members.
Ways to stand out from the crowd:
Broad knowledge with Video techniques, SOC architecture and Computer architecture is a big plus.
Strong programming skills in C/C++, SystemVerilog, Perl and Python is appreciated as a plus.