Member of Technical Staff, AI‑Optimized Memory Digital Design Engineer / Microarchitect
Micron · Folsom, CA
About this role
Micron is hiring a staff-level Hardware Engineer in the software engineering function based in Folsom, CA. The posting calls out experience with Python, C. Compensation is listed at $177,000–$309,000 per year.
- Role
- Hardware Engineer
- Function
- software engineering
- Level
- staff
- Track
- Individual contributor
- Employment
- Full-time
- Location
- Folsom, CA
- Posted
- May 19, 2026
More roles at Micron
Job description
from Micron careersOur vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Interested in changing the landscape of artificial intelligence workloads? Join our team where we are building next-generation, high-performance memory solutions for AI. In Micron's AI-optimized Memory Architecture organization, we partner closely with customers to design and deliver memory solutions purpose-built for emerging AI systems and applications.
As a Member of Technical Staff in the AI-optimized Architecture team, you will contribute to the microarchitecture and design of tightly coupled, high‑performance memory for AI. Apply expert knowledge to realize architecture features into silicon, with a strong focus on performance, power, area, (PPA) and reliability. This role is ideal for an engineer who combines deep digital design experience with strong architecture intuition, motivated by turning architectural intent into efficient, silicon‑proven implementations.
What you'll do
- Translate architecture requirements into efficient, scalable microarchitectures that optimize systems metrics with ownership from concept through implementation.
- Design, implement, and review SystemVerilog designs for memory systems architectures.
- Perform synthesis and early analysis to estimate and optimize area, power, and timing, and to guide architecture and microarchitecture tradeoffs.