Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

You will be part of the Heterogeneous Integration Group (HIG), owning chip-level static timing sign-off for next-generation die.
You will work closely with RTL design, physical design, architecture, design for test (DFT), verification, and product teams to ensure timing integrity from initial design through tape-out.
This is a hands-on senior technical role focused on chip-level static timing analysis ownership, timing closure, methodology development, and pre- and post-silicon timing correlation.

Job Description

Responsibilities will include, but are not limited to:

Own end-to-end chip-level static timing analysis and sign-off, covering all timing checks including setup, hold, recovery, removal, and data-to-data across all process corners, operating modes, and voltage and temperature conditions.
Develop, maintain, and validate comprehensive Synopsys Design Constraints (SDC) for all clock domains, reset trees, high-bandwidth memory (HBM) physical interfaces, Joint Test Action Group (JTAG), memory built-in self-test (MBIST), design for test (DFT), and configuration logic, ensuring sign-off quality and reuse across design generations.

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SOC Timing Analysis (STA) Engineer ,HBM

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Job description

Responsibilities will include, but are not limited to: