Senior / Principal DRAM Product Development Engineer – DEG Technology
Micron · Boise, ID
About this role
Micron is hiring a senior-level Hardware Engineer in the software engineering function based in Boise, ID. The posting calls out experience with Performance Optimization.
- Role
- Hardware Engineer
- Function
- software engineering
- Level
- senior
- Track
- Tech leadership
- Employment
- Full-time
- Location
- Boise, ID
- Posted
- May 19, 2026
More roles at Micron
Job description
from Micron careersOur vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Key Responsibilities
Technical Expertise & Design Enablement
Design, analyze, and verify memory, logic, and analog circuits across advanced technology nodes. Own and support major data path blocks including Sense Amplifiers, timing distribution, calibration, and training features. Identify design marginalities and recommend circuit-level or architectural solutions to improve DRAM robustness, yield, and performance.
Technology Development & Product Ramp
Enable new process node startup, qualification, yield learning, and production ramp. Provide technical guidance to Technology Development teams using strong process and device integration knowledge. Develop and track key metrics to assess technology readiness.
Verification, Silicon Bring-up & Yield
Support design verification and validation using CAD tools, modeling, and simulation. Define and execute silicon experiments and debug strategies in collaboration with Product Engineering. Perform electrical failure analysis of DRAM Array Sensing Schemes and lead yield improvement initiatives using statistical analysis.
Layout, Modeling & Optimization
Guide Sense Amp layout activities including floor planning, placement, routing, and layout reviews. Perform parasitic extraction and modeling to optimize signal margin and memory bit interaction of Sense Amps and Wordline drivers. Drive layout-aware optimization decisions to improve scalability and manufacturability.