senior operations Systems Engineer tech_leadership 5+ yrs Bachelor's · Posted Apr 20, 2026

About this role

Marvell is hiring a senior-level Systems Engineer in the operations function based in Ottawa, Canada. The posting calls out experience with Python, Linux, Backend Development, Cloud Computing and roughly 5+ years of relevant work. Listed education preference: a bachelor's degree or equivalent.

Role
Systems Engineer
Function
operations
Level
senior
Track
Tech leadership
Employment
Full-time
Location
Ottawa, Canada
Experience
5+ years
Education
Bachelor's degree
Posted
Apr 20, 2026
AI Summary
Senior Systems Engineer designs and develops optical Ethernet Transceiver ASICs for cloud infrastructure. Responsibilities include RTL development, synthesis, timing analysis, verification, and post-silicon debug. Requires 5+ years digital IC design experience at 16nm or smaller, proficiency in Verilog/SystemVerilog, and full ASIC flow knowledge.

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Job description

from Marvell careers

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

This is an existing vacancy.

Your Team, Your Impact

Optical PHY BU develops cutting-edge optical Ethernet Transceiver ASICs. Current online working and meetings that are through mediums such as Zoom and Webex are all based on cloud services. In order to respond to the dramatically increased demands of cloud-based connection capability, major cloud computing companies urgently demand faster and more secure internet connection components. One critical part of that component includes the optical ethernet transceiver ASICs. As a member of a digital hardware development team, the candidate will be assisting in chip design, verification, supporting back-end teams and timing closure.

What You Can Expect

  • Participate in various aspects of chip design RTL development, synthesis, static timing analysis, formal equivalence, RTL lint, cross clock domain (CDC) analysis and functional verification.
  • This is an excerpt. Read the full job description on Marvell careers →
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