CPU-SoC Mask Layout Designer

Job description

Job Description: 

In this position, you will be involving in the training, design and development of next generation SOC/CPU for wide range of Intel products. Your responsibilities will include some of the following but not limited to:

• Creates mask layouts of integrated circuits for a given specification and runs complete set of design verification tools for process design rules, electron migration, voltage drop (IR), ESD, and other reliability checks on the layouts.

• Creates accurate designs that meet project needs, applying understanding of design manuals, established processes, layout elements, and basic electronic principles.

• Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues.

• Designs and analyzes floorplans, power grid, and bumps and performs all required verification on the layout blocks.

• Troubleshoots a wide variety of issues up to and including layouts and tool/flow/methodology used in layout design.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position:

• Diploma in Electronic and Electrical Engineering or related major with good CGPA.

• Good communication skills and proficient in English

• Knowledge on Unix, VLSI Design, SOC/PC Architecture, System Verilog is major plus

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