Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal and/or highspeed IPs required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
Participates in the definition of architecture and microarchitecture features of the block being designed.
Applies various strategies, tools, and methods for mixed signal designs including analog behavior modeling and circuit simulation to write RTL and optimize mixed signal logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Supports SoC customers to ensure high quality integration of the IP block.

Qualifications:

Candidate must have a Bachelor, Master or PhD Degree in Computer Engineering, Electrical Engineering, Computer Science or related field.
Candidate will have 15 years of hands on experience with mixture of Logic Design and or PreSiliconVerification or DFX design.

Candidate must possess strong fundamentals on the following area.

Good understanding in SV, OVM, UVM and verification methodologies
Experience in using verification tools such as VCS DVE Verdi etc
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