Senior Physical Design Integration Engineer
Intel · Folsom, CA
About this role
Intel is hiring a senior-level Hardware Engineer in the software engineering function based in Folsom, CA. The posting calls out experience with Linux. Compensation is listed at $256,050–$361,480 per year.
- Role
- Hardware Engineer
- Function
- software engineering
- Level
- senior
- Track
- Individual contributor
- Employment
- Full-time
- Location
- Folsom, CA
- Posted
- May 18, 2026
More roles at Intel
Job description
from Intel careersJob Description:
At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers.
The Physical Design Integration Engineer performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing.
Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.