Senior Formal Verification Engineer – AI SoC Development
Intel · Folsom, CA
About this role
Intel is hiring a senior-level Embedded Software Engineer in the software engineering function based in Folsom, CA. The posting calls out experience with Python, Testing and roughly 10+ years of relevant work. Listed education preference: a bachelor's degree or equivalent. Compensation is listed at $220,920–$311,890 per year.
- Role
- Embedded Software Engineer
- Function
- software engineering
- Level
- senior
- Track
- Individual contributor
- Employment
- Full-time
- Location
- Folsom, CA
- Experience
- 10+ years
- Education
- Bachelor's degree
- Posted
- Apr 20, 2026
More roles at Intel
Job description
from Intel careersJob Description:
Intel’s AI SoC organization is driving innovation in next-generation ASICs for AI applications across edge and cloud. As a Senior Formal Verification Engineer, you will play a critical role in ensuring the functional correctness of complex digital designs using advanced formal methods. This position offers the opportunity to work on cutting-edge technology and shape verification strategies for AI SoCs.
Key Responsibilities
- Own formal verification strategy and execution for complex SoC IP blocks and subsystems.
- Develop and maintain formal verification environments using SystemVerilog Assertions (SVA) and industry-standard formal tools.
- Write and review formal properties, constraints, and coverage goals to achieve exhaustive verification.
- Collaborate with design and simulation teams to identify corner cases and complement dynamic verification.
- Drive formal sign-off, including convergence analysis and coverage closure.
- Contribute to pre-silicon verification, chip bring-up, and post-silicon debug support.
- Mentor junior engineers and establish best practices for formal verification methodology
Additional Responsibilities
- Define and develop scalable, reusable verification plans for block, subsystem, and SoC levels.
- Execute verification plans and run emulation and system simulation models to validate design, analyze power/performance, and uncover bugs.
- Debug and root-cause issues in the presilicon environment; implement corrective measures.
- Collaborate with architects, RTL developers, and physical design teams to improve verification of complex features.